The present invention relates generally to electronic packaging and a method of manufacturing for same, and more particularly, to electrical interconnections between a ceramic substrate carrier and a supporting circuit board, and a process for making such electrical interconnections.
State-of-the-art electronic packaging generally contains many levels of packages and interconnections. The first level package may connect one or more silicon chips on a ceramic substrate carrier. A second level package may interconnect one or more such ceramic substrate carriers on an organic board. In order to achieve high conductivity for power distribution, desirable low electrical inductance for high speed and low noise, proper mechanical properties for acceptable mechanical support, and fatigue characteristics, as well as manufacturability considerations, heretofore ceramic substrate carriers are usually provided with rigid metal pins which are brazed on the ceramic with a suitable braze material such as a gold-tin alloy. Ceramic substrates with such rigid pins are subsequently plugged into a connector or wave soldered to an array of plated through holes on the organic board. The foregoing described connection system has disadvantages of high cost associated with the braze material, the rigid metal pins, the pin connectors or plated through holes, which holes also limit the number of wiring channels available in the board.
IBM Technical Disclosure Bulletin, Vol. 33, No. 2, July 1990, p. 253, the disclosure of which is incorporated by reference herein, proposes an electrical interconnection structure wherein a ceramic carrier and printed circuit board are joined by superplastic solder columns to form a thermal fatigue-resistant joint. The solder columns are actually bonded to the ceramic carrier and printed circuit board by a lower melting solder. As shown in FIG. 1A of this reference, the solder columns are loaded into a graphite fixture which sits upon the ceramic carrier which has previously been screened with the lower melting solder. After solder reflow, the graphite fixture is removed.
The present inventors have discovered, however, that such a fabrication process results in uneven height of the solder columns. There are several reasons for this. One reason is that the solder columns may not all be cut to the same dimension. Another reason is that during reflow, the solder columns are partially supported by the lower melting solder; if the amount of lower melting solder varies from site to site, the solder columns will have different heights. It is desirable to have all solder columns of the same height for maximum thermal fatigue resistance and to insure that the electrical integrity of each Joint is maintained.
Behun et al. U.S. Pat. No. 4,914,814, the disclosure of which is incorporated by reference herein, discloses an in-situ method of forming the solder columns on metallized pads of the ceramic carrier by melting a plurality of solder balls in a graphite mold. Thereafter, the solder columns can be joined to an organic board.
Lakritz et al. U.S. Pat. No. 4,545,610, the disclosure of which is incorporated by reference herein, discloses an in-situ method of forming solder columns between a semiconductor device and a ceramic substrate. Solder portions are formed between the device and carrier. After reflow, columns are formed. To prevent the columns from collapsing during reflow and to maintain proper spacing between the joined parts, stand-offs are placed between the device and carrier.
Allen et al. U.S. Pat. No. 4,705,205, the disclosure of which is incorporated by reference herein, discloses a method of joining two electronic components which may be, for example, a chip carrier and an organic board. Solder preforms (e.g., columns) are placed in a retaining member and the solder preforms are then joined to at least one of the electronic components. The retaining member remains its shape at the temperatures encountered during the joining operation. The retaining member may stay in place after joining or may be made of a material which facilitates its removal after joining.
Accordingly, it is a purpose of the present invention to provide a process for fabricating an array of high density electrical interconnections between a ceramic carrier and a supporting circuit board.
It is also a purpose of the present invention to provide a relatively low cost process for fabricating electrical interconnections between a ceramic carrier and a supporting circuit board.
It is a further purpose of the present invention to provide an improved electrical interconnection for electronic packaging.
It is yet another purpose of the present invention to provide an improved electrical interconnection which could withstand the stresses associated with thermal expansion mismatch between a ceramic carrier and a supporting circuit board.
These and other purposes of the invention will become more apparent after referring to the following description considered in conjunction with the accompanying drawings.